Writing testbenches in UVM
Understanding usage of Configuration db in UVM
Strategies for implementation of UVM components such as Transaction, Generator, Sequencer, Monitor, Scoreboard, Environment, Test
Usage of TLM ports for Communication between Driver , Sequencer, Monitor, Scoreboard
Usage of Reporting Mechanism in UVM
Usage of Virtual Interface
Usage of the Base Classes viz. UVM_Object and UVM_Component
Pure Lab-based course with minimum focus on theoretical aspects of UVM
