VSD - Static Timing Analysis - II For Free
What you’ll learn
Students will be able to do a real full chip static timing analysis with $0 spent, as designs and tools used in this course are opensource
Students will be able to appreciate power of opensource EDA tools, like Opentimer used in this course, and help in contributing towards the development
Students can explore commercial tools with knowledge and concepts from this course, quite easily
Manage a entire chip timing signoff
Requirements
Static Timing analysis - part 1 course needs to be fully completed to start this course. No exceptions
Knowledge of physical design flow and clock tree synthesis will be helpful
Who this course is for:
Anyone who has completed static timing analysis - part 1 course
Anyone (with 100% static timing analysis - part 1 course completed) who has basic knowledge on flipflops, gates and digital logic
